The large image: This week on the annual Hot Chips occasion, an enthusiastic Pat Gelsinger talked in regards to the subsequent chapter of microarchitecture design at Intel. It’s all about Foveros, a 3D packaging know-how that can give Intel faster ft in an ever tougher semiconductor panorama.
Intel’s Thirteenth-gen Core processors are on the horizon, however they should not stray too removed from their predecessors relating to microarchitecture. After all, Intel makes use of the identical Intel 7 node as Alder Lake CPUs, so there is not a lot to be enthusiastic about — save for increased clocks and higher overclocking capabilities.
Meanwhile, Team Blue has been engaged on a way more thrilling structure referred to as Meteor Lake, which can characteristic a chiplet configuration. Unlike rival AMD, Intel has been extra reluctant to maneuver away from monolithic, system-on-chip designs and thus far solely applied the a number of module strategy with server processors just like the Sapphire Rapids household and compute accelerator GPUs just like the Ponte Vecchio lineup.
That stated, the corporate is nicely conscious that the way forward for semiconductors lies in system-on-package chip architectures as a substitute of cramming extra transistors onto a single chip. To that finish, Intel is working with corporations like AMD, Arm, Samsung, Qualcomm, Google, TSMC, and others to outline a brand new trade commonplace referred to as Universal Chiplet Interconnect Express (UCIe). The transfer will pave the best way for system producers to combine and match elements from varied distributors simply.
Meteor Lake is the right event for Intel to begin delivering on guarantees made when CEO Pat Gelsinger took the helm. One: It will depart AMD within the rearview mirror, and two: It will meet up with Apple’s M-series silicon. Gelsinger not too long ago spoke about this and extra on the Hot Chips 34 convention, bringing the corporate’s renewed technique into focus.
Each Meteor Lake bundle will characteristic 4 chiplets, with just one from an Intel foundry. The firm will manufacture the first module utilizing an Intel 4 course of node, whereas TSMC will manufacture the opposite three, presumably on as many as three completely different nodes.
While this will seem to be an costly and complex strategy, breaking down a big monolithic design into chiplets affords higher yields and extra flexibility when selecting the optimum course of know-how for the CPU, GPU, I/O Expander, and SoC tiles. These modules are linked utilizing a know-how that Intel may also use for Arrow Lake and Lunar Lake processors — 3D Foveros.
You could recall Intel first demonstrating a 3D packaging know-how for logic chips about three and a half years in the past. A key characteristic of Foveros is the face-to-face, chip-on-chip bonding it achieves utilizing tiny, 36-micron bumps. This method permits producers to stack chips like pancakes for higher efficiency and decrease energy consumption.
The first-generation Foveros interposer will increase bandwidth by double or triple in comparison with a silicon interposer and scales from three-watt designs as much as a whopping one kilowatt. Like the short-lived Lakefield CPUs, Intel makes this interposer utilizing a singular 22FFL course of optimized for power effectivity.
It’s additionally value noting Intel plans to make use of Foveros along with its 2.5D, Embedded Multi-Die Interconnect Bridge (EMIB) know-how, utilized in its Stratix and Agilex FPGA product households to attach adjoining dies on a 2D airplane. The firm already leverages these packaging methods in its Sapphire Rapids CPUs, which we count on to ship to information middle clients later this yr. The similar is true for Ponte Vecchio GPUs, which can supposedly be 2.5 instances extra highly effective than Nvidia’s A100 if we go by Intel’s numbers.
Ponte Vecchio packs over 100 billion transistors throughout 47 chiplets and may pump out as much as 52 teraflops of FP32/FP64 compute. Still, Intel has increased ambitions for packing much more energy in future designs utilizing Foveros and EMIB.
Gelsinger says the corporate needs to realize one trillion transistors in a single bundle by 2030, and it is already making steps in that path with applied sciences like Foveros Omni and Forveros Direct. In concept, Intel may ultimately use hybrid bonding interconnects with 1-micron bumps and blend a number of prime die tiles with bases produced on completely different course of nodes. It expects quantity manufacturing by subsequent yr.
Meteor Lake shoppers ought to profit from extra highly effective {hardware} at close to the identical value regardless of the added complexity. Intel is just now diving into quantity manufacturing of shopper merchandise utilizing 3D Foveros packaging. However, the corporate is assured it could actually ship CPUs that value the identical or much less in comparison with monolithic, single-die options.
While Intel does not go into nice element in regards to the efficiency we are able to count on from the Foveros interconnect tile, we’re informed this know-how is designed to run at “a number of GHz” even in a passive configuration. There are even rumors that 14th-gen processors will combine ray tracing capabilities, however we’ll have to attend and see. AMD has had loads of success with chiplet designs, so will probably be fascinating to see how nicely Intel can execute when following an identical route.
Furthermore, the power to combine and match tiles made on mature and modern course of nodes offers Intel a bonus on the foundry providers entrance, the place it plans to make fast progress within the coming years. Team Blue can profit from TSMC’s EUV experience whereas engaged on incorporating extra EUV methods into its personal course of tech.
Image credit score: PCWatch